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#include <reg52.h>
#include <stdio.h>
#include <sys.h>
#include "at45_drv.h"
#include <intrins.h>
#define LOW 0
#define HIGH 1
#define BUSY 2
#define OK 3
#define ARRAY_SIZE 264
sbit SCLK = P1^0;
sbit MOSI = P1^1;
sbit MISO = P1^2;
sbit CS = P1^3;
sbit WP = P2^0;
sbit RESET = P2^1;
void Enable_at45()
{
SCLK = 1;
CS = 0;
Nop();
Nop();
}
void Disable_at45()
{
CS = 1;
}
void Init_at45()
{
uchar i,j;
Enable_at45();
RESET = 0;
SCLK = 1;
MOSI = 1;
MISO = 1;
WP = 1;
WP = 0;
for(i=0;i<255;i++)
{
for(j=0;j<255;j++);
}
RESET = 1;
}
uchar Read_one_bit()
{
uchar temp;
SCLK = LOW;
Nop();Nop();
SCLK = HIGH;
Nop();
//SCLK = LOW;
MISO = HIGH;
temp = MISO;
SCLK = LOW;
return temp;
}
uchar Read_one_byte()
{
uchar temp_data = 0 ,i;
for(i=0;i<8;i++)
{
temp_data = temp_data << 1;
if(Read_one_bit()!= 0)
temp_data = temp_data | 0x01;
}
return temp_data;
}
void send_one_bit(uchar temp)
{
SCLK = LOW;
if(temp)
MOSI = HIGH;
else MOSI =LOW;
SCLK = HIGH;
Nop();Nop();
SCLK = LOW;
}
void send_one_byte(uchar d)
{
uchar i = 0;
uchar temp_data;
temp_data = d;
for(i = 0;i < 8;i ++)
{
if(temp_data & 0x80)
send_one_bit(1);
else
send_one_bit(0);
temp_data = temp_data << 1;
}
}
#define READ_RS_CMD 0xD7 //SPI MODE3读状态寄存器命令
uchar Read_RS() /*读状态寄存器*/
{
uchar temp_data;
//Init_at45();
Enable_at45();
send_one_byte(READ_RS_CMD);
temp_data = Read_one_byte();
//SCLK = 0;
Disable_at45();
return temp_data;
}
#define ERASE_BLOCK_CMD 0x50
bit Erase_block(uchar block_addr)
{
uchar temp_addr;
Enable_at45();
send_one_byte(ERASE_BLOCK_CMD);
temp_addr = block_addr & 0x70;
temp_addr = temp_addr >> 4;
send_one_byte(temp_addr);
temp_addr = block_addr & 0x0f;
temp_addr = temp_addr << 4;
send_one_byte(temp_addr);
send_one_byte(0x00);
Disable_at45();
for(temp_addr=0;temp_addr<20;temp_addr++)
{
if(Read_RS()&0x80)
return true;
Delay10ms();
}
return false;
}
#define BUFF_WRITE_CMD 0x84
#define MAIN_WRITE_CMD 0x83
bit Page_write(uint page_addr,uint byte_addr,uchar *s,uint len)
{
uint i;
uchar temp_addr;
if((len+byte_addr)>264)
return false;
Enable_at45();
send_one_byte(BUFF_WRITE_CMD);
send_one_byte(0x00);
temp_addr = (uchar)((byte_addr&0xf00)>>8);
send_one_byte(temp_addr);
temp_addr = (uchar)(byte_addr&0x0ff);
send_one_byte(temp_addr);
for(i=0;i<len;i++)
{
send_one_byte(*s);
s++;
}
Disable_at45();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Nop();
Enable_at45();
send_one_byte(MAIN_WRITE_CMD);
temp_addr = (uchar)((page_addr&0xf80)>>7);
send_one_byte(temp_addr);
temp_addr = (uchar)((page_addr&0x07f)<<1);
send_one_byte(temp_addr);
send_one_byte(0x00);
Disable_at45();
for(temp_addr=0;temp_addr<100;temp_addr++)
{
Delay10ms();
}
for(temp_addr=0;temp_addr<10;temp_addr++)
{
if(Read_RS()&0x80)
return true;
Delay10ms();
}
return false;
}
#define ARRAY_READ_CMD 0xe8
bit Array_read(long addr,uchar *s,uint len)
{
uint page_addr;
uint byte_addr;
uchar temp_addr;
// if(addr>2112*128)
// return false;
page_addr = addr/264;
byte_addr = addr%264;
Enable_at45();
send_one_byte(ARRAY_READ_CMD);
temp_addr = (uchar)((page_addr&0xf80)>>7);
send_one_byte(temp_addr);
temp_addr = (uchar)((page_addr&0x07f)<<1);
if(byte_addr&0xf00)
temp_addr = temp_addr | 0x01;
send_one_byte(temp_addr);
temp_addr = (uchar)(byte_addr&0x0ff);
send_one_byte(temp_addr);
send_one_byte(0x00);
send_one_byte(0x00);
send_one_byte(0x00);
send_one_byte(0x00);
for(byte_addr=0;byte_addr<len;byte_addr++)
{
*s = Read_one_byte();
s++;
}
Disable_at45();
return true;
} |
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