-
常用电阻值[转贴]
2008-03-19 21:23:48
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AD7705的Meag16单片机源程序[转贴]
2008-03-05 19:27:03
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AD7705应用 C51源程序[转贴]
2008-03-05 19:16:55
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AD7707 PIC程序
2008-03-03 21:29:29
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老和尚：我早已经把她放下了，你怎么还没放下呢
2008-02-20 20:03:59
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VC命名规则[转载]
2008-02-19 10:04:47
-
可用的来电显示指令AT+CLIP=1;
2008-02-16 19:45:46
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PADS技巧[转贴]
2008-02-15 17:41:58
-
一些AD，DA的术语[转贴自TI]
2008-02-12 17:02:09
原文件地址：http://www.maxim-ic.com.cn/appnotes.cfm/an_pk/641
ADC and DAC Glossary
Abstract: This document collects and defines technical terms commonly used with analog-to-digital converters (ADCs) and digital-to-analog converters (DACs).
Acquisition Time
Acquisition time is the interval between the release of the hold state (imposed by the input circuitry of a track-and-hold) and the instant at which the voltage on the sampling capacitor settles to within 1 LSB of a new input value. The equation for acquisition time (Tacq) is:
where RSOURCE is the source impedance, CSAMPLE is the sampling capacitance, and N is the number of resolution bits.
Aliasing
In sampling theory, input-signal frequencies that exceed the Nyquist frequency are "aliased." That is, they are "folded back" or replicated at other positions in the spectrum above and below the Nyquist frequency. To prevent aliasing, you must adequately filter all undesired signals so the ADC does not digitize them. Aliasing can be used to advantage when undersampling.
See also application note Filter Basics: Anti-Aliasing
Aperture Delay
Aperture delay (tAD) in an ADC is the interval between the sampling edge of the clock signal (the rising edge of the clock signal in the figure) and the instant when the sample is taken. The sample is taken when the ADC's track-and-hold goes into the hold state.
Aperture delay (red) and jitter (blue).
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the aperture delay, as shown in this figure. Typical ADC aperture jitter values are much smaller than those of aperture delay.
Binary Coding (Unipolar)
Straight binary is a coding scheme typically used for unipolar signals. The binary code (zero scale to full scale) ranges from all zeros (00...000) to the positive full-scale value of all ones (11...111). Midscale is represented by a one (the MSB) followed by all zeros (10...000). This code is similar to offset binary coding, which accommodates the positive and negative values of bipolar transfer functions.
Bipolar Inputs
The term 'bipolar' indicates that the signal swings above and below some reference level. In single-ended systems, the input is typically referenced to analog ground, so a bipolar signal is one that swings above and below ground. In differential systems, where the signal is not referenced to ground but where the positive input is referenced to the negative input, a bipolar signal is one in which the positive input swings above and below the negative input.
Common-Mode Rejection (CMR)
Common-mode rejection is the ability of a device to reject a signal that is common to both inputs. The common-mode signal can be an AC or DC signal, or a combination of the two. Common-mode rejection ratio (CMRR) is the ratio of the differential signal gain to the common-mode signal gain. CMRR is often expressed in decibels (dB).
Crosstalk
Crosstalk is a measure of how well each analog input is isolated from the others. For an ADC with more than one input channel, crosstalk is the amount of signal that couples from one analog input into another. This value is typically specified in decibels (dB). For a DAC with more than one input channel, crosstalk is the amount of noise that appears on a DAC output when another DAC output channel is updated.
Differential Nonlinearity (DNL) Error
For an ADC, the analog-input levels that trigger any two successive output codes should differ by one LSB (DNL = 0). Any deviation from one LSB is defined as DNL. For a DAC, DNL error is the difference between the ideal and the measured output responses for successive DAC codes. An ideal DAC response would have analog output values exactly one code (LSB) apart (DNL = 0). (A DNL specification of greater than or equal to 1LSB guarantees monotonicity.) (See "Monotonic.")
DNL for an ADC and a DAC.
See also application note INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs)
Digital Feedthrough
Digital feedthrough is the noise that appears on a DAC output when the digital control lines are toggled. In the figure, feedthrough on the DAC output is the result of noise from the serial clock signal.
Digital feedthrough.
Dynamic Range
Typically expressed in dB, dynamic range is defined as the range between the noise floor of a device and its specified maximum output level. An ADC's dynamic range is the range of signal amplitudes which the ADC can resolve; an ADC with a dynamic range of 60dB can resolve signal amplitudes from x to 1000x. Dynamic range is important in communication applications, where signal strengths vary dramatically. If the signal is too large, it over-ranges the ADC input. If the signal is too small, it gets lost in the converter's quantization noise.
Effective Number Of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists only of quantization noise. As the input frequency increases, the overall noise (particularly in the distortion components) also increases, thereby reducing the ENOB and SINAD. (See 'Signal-to-Noise and Distortion Ratio (SINAD).') ENOB for a full-scale, sinusoidal input waveform. is computed from:
Force-Sense Outputs
This is a measurement technique in which a voltage (or current) is forced at a remote point in a circuit, and the resulting current (or voltage) is measured (sensed). DACs with integrated output amplifiers, for example, sometimes include force-sense outputs. The inverting input of the output amplifier is available for external connection, and the feedback path must be closed externally.
Full-Power Bandwidth (FPBW)
An ADC is operated with an applied analog input at or near the converter's specified full-scale amplitude. The input frequency is increased to the point at which the amplitude of the digitized conversion result has decreased by 3dB. That input frequency is defined as the full-power input bandwidth.
Full-Scale (FS) error
Full-scale error is the difference between the actual value that triggers the transition to full-scale and the ideal analog full-scale transition value. Full-scale error equals offset error + gain error, as shown in this figure.
Full-scale error for an ADC and a DAC.
FS Gain Error (DACs)
The full-scale gain error of an digital-to-analog converter (DAC) is the difference between the actual and the ideal output span. The actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. The full-scale gain error of any data converter can be affected by the choice of reference used to measure the gain error.
Gain Error
The gain error of an ADC or DAC indicates how well the slope of an actual transfer function matches the slope of the ideal transfer function. Gain error is usually expressed in LSB or as a percent of full-scale range (%FSR), and it can be calibrated out with hardware or in software. Gain error is the full-scale error minus the offset error.
Gain error for an ADC and a DAC.
Gain Error Drift
Gain-error drift is the variation in gain error due to a change in ambient temperature, typically expressed in ppm/°C.
Gain Matching
Gain matching indicates how well the gains of all channels in a multichannel ADC are matched to each other. To calculate gain matching, apply the same input signal to all channels, and report the maximum deviation in gain, typically in dB.
Glitch Impulse
Glitch impulse is the voltage transient that appears at the DAC output when a major-carry transition occurs. Typically measured as nV•s, it equals the area under the curve on a voltage-vs-time graph.
Harmonic
A harmonic of a periodic signal is a sinewave multiple of the signal's fundamental frequency.
Integral Nonlinearity (INL) Error
For data converters, INL is the deviation of an actual transfer function from a straight line. After nullifying offset and gain errors, the straight line is either a best-fit straight line or a line drawn between the end points of the transfer function. INL is often called 'relative accuracy.'
See also application note INL/DNL Measurements for High-Speed Analog-to-Digital Converters (ADCs).
INL for an ADC and a DAC.
Intermodulation Distortion (IMD)
IMD is a phenomenon in which nonlinearity in a circuit or device creates new frequency components not in the original signal. IMD includes the effects of harmonic distortion and two-tone distortion. It is measured as the total power of those selected intermodulation products (i.e., IM2 through IM5) to the total power of the two input signals, f1 and f2. The signals f1 and f2 are of equal amplitude and very close to one another in frequency. The 2nd- to 5th-order intermodulation products are as follows:- 2nd-order intermodulation products (IM2): f1 + f2, f2 - f1
- 3rd-order intermodulation products (IM3): 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1
- 4th-order intermodulation products (IM4): 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1
- 5th-order intermodulation products (IM5): 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1.
Least Significant Bit (LSB)
In a binary number, the LSB is the least weighted bit in the group. Typically, the LSB is the furthest right bit. For an ADC or DAC, the weight of an LSB equals the full-scale voltage range of the converter divided by 2N, where N is the converter's resolution. For a 12-bit ADC with a unipolar full-scale voltage of 2.5V, 1LSB = (2.5V/212) = 610µV
Major-Carry Transition
At the major-carry transition (around mid-scale), either the MSB changes from low to high and all other bits change from high to low, or the MSB changes from high to low and all other bits change from low to high. For example, 01111111 to 10000000 is a major-carry transition. Major-carry transitions often produce the worst switching noise. (See Glitch Impulse.)
Monotonic
A sequence increases monotonically if for every n, Pn + 1 is greater than or equal to Pn. Similarly, a sequence decreases monotonically if for every n, Pn + 1 is less than or equal to Pn. A DAC is monotonic if the analog output always increases as the DAC-code input increases. An ADC is monotonic if the digital output code always increases as the ADC analog input increases. A converter is guaranteed monotonic if the DNL error is no greater than ±1LSB
Most Significant Bit (MSB)
In a binary number, the MSB is the most weighted bit in the number. Typically, the MSB is the left-most bit.
Multiplying DAC (MDAC)
A multiplying DAC allows an AC signal to be applied to the reference input. By feeding the signal of interest into the reference input and by using the DAC codes to scale the signal, the DAC can be used as a digital attenuator.
No Missing Codes
An ADC has no missing codes if it produces all possible digital codes in response to a ramp signal applied to the analog input.
Nyquist Frequency
The Nyquist principle states that, to allow an analog signal to be completely represented with no aliasing effects, the ADC's sampling rate must be at least twice the maximum bandwidth of the signal. This maximum bandwidth is called the Nyquist frequency.
Offset Binary Coding
Offset binary is a coding scheme often used for bipolar signals. In offset binary coding, the most negative value (negative full scale) is represented by all zeros (00...000) and the most positive value (positive full scale) is represented by all ones (11...111). Zero-scale is represented by a one (MSB) followed by all zeros (10...000). This scheme is similar to straight binary coding, which is typically used for unipolar signals. (See Binary Coding, Unipolar.)
Offset Error (Bipolar)
The measurement of offset error in bipolar converters is similar to that of offset error in unipolar converters. However, the error measured at zero-scale is at the midpoint of the bipolar transfer functions. (See Offset Error (Unipolar).)
Offset Error (Unipolar)
Offset error, often called 'zero-scale' error, indicates how well the actual transfer function matches the ideal transfer function at a single point. For an ideal data converter, the first transition occurs at 0.5LSB above zero. For an ADC, the zero-scale voltage is applied to the analog input and is increased until the first transition occurs. For a DAC, offset error is the analog output response to an input code of all zeros.
Offset error for an ADC and a DAC.
Offset Error Drift
Offset-error drift is the variation in offset error due a change in ambient temperature, typically expressed in ppm/°C.
Oversampling
For an ADC, sampling the analog input at a rate much higher than the Nyquist frequency is called oversampling. Oversampling improves the ADC's dynamic performance by effectively reducing its noise floor. Improved dynamic performance leads, in turn, to higher resolution. Oversampling is the basis of sigma-delta ADCs.
See also application note Demystifying Sigma-Delta ADCs
Phase-Matching
Phase matching indicates how well matched are the phases of identical signals applied to all channels in a multichannel ADC. Phase matching is the maximum deviation in phase among all the channels, and is typically reported in degrees.
Power-Supply Rejection (PSR)
Power Supply Rejection Ratio (PSRR) is the ratio of the change in DC power supply voltage to the resulting change in full-scale error, expressed in dB.
Quantization Error
For an ADC, quantization error is defined as the difference between the actual analog input and the digital representation of that value. (See 'Quantization.')
Ratiometric Measurement
Instead of a constant-valued reference voltage, a fraction of the signal applied to the transducer (i.e., the load cell or bridge) is applied to the ADC's voltage reference input. This type of measurement, called ratiometric, eliminates any errors introduced by changes in the reference voltage. An example of ratiometric measurement using a resistive bridge is shown in the figure below.
Ratiometric measurement using resistive bridge network.
Resolution
ADC resolution is the number of bits used to represent the analog input signal. To more accurately replicate the analog signal, you must increase the resolution. Using an ADC with higher resolution also reduces the quantization error. For DACs, resolution is similar but reversed—incrementing the code applied to a higher resolution DAC produces smaller step sizes in the analog output.
Root Mean Square (RMS)
2/2 (or 0.707) times the peak value, which is 0.354 times the peak-to-peak value.
Sampling Rate/Frequency
Sampling rate or sampling frequency, specified in samples per second (sps), is the rate at which an ADC acquires (samples) the analog input. For ADCs that perform. one sample per conversion (such as SAR, flash, and pipeline ADCs), the sampling rate is also referred to as the throughput rate. For sigma-delta ADCs, the sampling rate is typically much higher than the output data rate.
Settling Time
For a DAC, settling time is the interval between a command to update (change) its output value and the instant it reaches its final value, within a specified percentage. Settling time is affected by the slew rate of an output amplifier and by the amount of amplifier ringing and signal overshoot. For an ADC, it is essential that the time required for voltage on the sampling capacitor to settle to within 1 LSB be less than the converter's acquisition time.
Signal-to-Noise And Distortion (SINAD)
SINAD is the ratio of the RMS value of the sinewave (input for an ADC, or reconstructed output for a DAC) to the RMS value of the converter noise plus distortion (without the sinewave). RMS noise plus distortion includes all spectral components up to the Nyquist frequency, excluding the fundamental and the DC offset. SINAD is typically expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the amplitude of the desired signal to the amplitude of the noise signals at a given point in time. For a waveform. perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error).The ideal, theoretical minimum ADC noise is caused by quantization error only and results directly from the ADC's resolution (N bits):
(Actual ADCs produce thermal noise, reference noise, clock jitter, etc., in addition to quantization noise.)
Signed Binary Coding
Signed binary is a coding scheme in which the MSB represents the sign (positive or negative) of a binary number. Thus, the 8-bit representation of -2 is 10000010, and the representation of +2 is 00000010.
Slew Rate
Slew rate is the maximum rate at which a DAC output can change, or the maximum rate at which an ADC's input can change without causing an error in the digitized output. For a DAC with output amplifier, the specified slew rate is typically that of the amplifier.
Small-Signal Bandwidth (SSBW)
To measure SSBW, apply to an ADC an analog input signal of sufficiently small amplitude that its slew rate does not limit the ADC performance. Then, sweep the input frequency up to the point where the amplitude of the digitized conversion result decreases by -3dB. SSBW is often limited by the performance of the associated track-and-hold amplifier.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. SFDR is specified in decibels relative to the carrier (dBc).
Total Harmonic Distortion (THD)
THD measures the distortion content of a signal, and is specified in decibels relative to the carrier (dBc). For ADCs, THD is the ratio of the RMS sum of the selected harmonics of the input signal to the fundamental itself. Only harmonics within the Nyquist limit are included in the measurement.
Track-and-Hold
Track-and-hold, often called 'sample-and-hold,' refers to the input-sampling circuitry of an ADC. The most basic representation of a track-and-hold input is an analog switch and a capacitor. (See figure.) The circuit is in 'track' mode when the switch is closed. When the switch opens, the last instantaneous value of the input is held on the sampling capacitor, and the circuit is in 'hold' mode.
Basic track-and-hold.
Transition Noise
Transition noise is the range of input voltages that cause an ADC output to toggle between adjacent output codes. As you increase the analog input voltage, the voltages that define where each code transition occurs (code edges) are uncertain due to the associated transition noise.
Two's Complement Coding
Two's complement is a digital coding scheme for positive and negative numbers that simplifies addition and subtraction computations. In this scheme, the 8-bit representation of -2 is 11111110, and the representation of +2 is 00000010.
Undersampling
Undersampling is a technique in which the ADC sampling rate is lower than the analog input frequency?a condition that causes aliasing. Given the Nyquist criterion, it is natural to expect that undersampling would result in a loss of signal information. However, with proper filtering of the input signal and with proper selection of the analog input and sampling frequencies, the aliased components that contain the signal information can be shifted from a higher frequency to a lower frequency and then converted. This method effectively uses the ADC as a downconverter, shifting higher-bandwidth signals into the ADC's desired band of interest. For this technique to be successful, the bandwidth of the ADC's track-and-hold must be capable of handling the highest frequency signals anticipated.
Unipolar
For an ADC with single-ended analog input, the unipolar input ranges from zero-scale (typically ground) to full scale (typically the reference voltage). For an ADC with differential inputs, the unipolar input ranges from zero-scale to full-scale, with the input measured as the positive input with respect to the negative input.
Zero-Scale Error
See offset error (unipolar). -
关于SPI口和AT45DB081连接的问题！[转贴]
2008-02-03 22:17:36
-
ARM注意事项
2008-02-03 21:59:15
-
LPC ARM SPI0改成16位的
2008-02-03 17:54:19
-
另一个更详细的AT指令集列表
2008-01-10 23:44:51
-
at信息[转贴]
2008-01-10 23:27:34
AT指令測試成功 (外接式GPRS mode)
ASCI碼指令
功能
手機回答
AT回車
握手
OK
ATE
簡化顯示
OK
AT+CLCC
來電顯示
OK 來電話時串口輸出：RING
AT+CNMI
新資訊指示。這個命令選擇如何從網路上接收短資訊
AT+CNMI=1,1,2
設置收到短消息提示
OK
+CMTI：“SM”，4
4表示手機內短消息數量
AT+CMGL
列出SIM卡中的短消息PDU/text
0/「REC UNREAD」-未讀
1/「REC READ」-已讀
2/「STO UNSENT」-待發
3/「STO SENT」-已發
4/「ALL」-全部的）
AT+CMGL=0
讀取電話上全部未讀過的SMS消息
AT+CMGL=4
讀取全部SMS消息
AT+CMGR=X回車
讀取第X條短消息。資訊從+CPMS命令設定的記憶體讀取
AT+CMGF=0回車
用PDU格式
AT+CMGD=X回車
刪除第X條短消息
AT+CLIP=1,1
來電自動顯示的指令
ERROR
來電話！
RING +CLIP: 13306285091,129
AT+CMGR=1
讀取第1條短信
0：未讀過，新的短資訊
1：已讀過
第二個1表示已讀
150 表示PDU資料的長度
1 表示讀取第幾條短信
+CMGR: 1,1,,150
AT+CMGW
向SIM內存中寫入待發的短消息
AT+CSCA
短消息中心地址
AT+CSCB
選擇蜂窩廣播消息
AT+CSMS
選擇短消息服務。支援的服務有GSM-MO、SMS-MT、SMS-CB
AT+CSDH
顯示文本方式的參數
ATD
撥號命令。這個命令用來設置通話、資料或傳真呼叫
ATH
掛機命令
ATA
接電話
AT+CEER
擴展錯誤報告。這個命令給出當上一次通話設置失敗後中斷通話的原因。
AT+CSNS
單一編號方案
用外接式GPRS mode之測試結果：
AT+CMGL ：列出SIM卡中的短消息PDU/text：
0/「REC UNREAD」-未讀，
1/「REC READ」-已讀，
2/「STO UNSENT」-待發，
3/「STO SENT」-已發，
4/「ALL」-全部的）
送出： AT+CMGL=0 //讀取電話上全部未讀過的SMS消息
傳回： OK //已經都讀取過
送出：AT+CMGL=1 //已讀
傳回：
+CMGL: 1,1,,23
0791889623048014040C918896122907300000705051412285230461F8B90D
+CMGL: 2,1,,25
0791889623048014040C9188961229073000007050514114402306EF
+CMGL: 26,1,,155
0791889623048014040C9188961115106900087040510100742388833256E
D
2563D
AA
623002
OK
另一个更详细的AT指令集[转贴]
2008-01-10 23:25:34
at+vcid来电显示
2008-01-10 23:05:40
74HC164数码显示程序[转贴]
2007-12-30 17:34:31
74系列芯片功能大全[转贴]
2007-12-27 11:14:10
7400TTL2输入端四与非门7401TTL集电极开路2输入端四与非门7402TTL2输入端四或非门7403TTL集电极开路2输入端四与非门7404TTL六反相器7405TTL集电极开路六反相器7406TTL集电极开路六反相高压驱动器7407TTL集电极开路六正相高压驱动器7408TTL2输入端四与门7409TTL集电极开路2输入端四与门7410TTL3输入端3与非门74107TTL带清除主...
同型号的74系列、74HC系列、74LS系列芯片，逻辑功能上
一样的。74LSxx、74HCxx的使用说明可
阅74xx的使用说明。 有些型号里包含了几种型号，如74HC161资料里包含了74HC160、74HC161、74HC162、74HC163四种芯片的功能。
7400 TTL 2输入端四与非门
7401 TTL 集电极开路2输入端四与非门
7402 TTL 2输入端四或非门
7403 TTL 集电极开路2输入端四与非门
7404 TTL 六反相器
7405 TTL 集电极开路六反相器
7406 TTL 集电极开路六反相高压驱动器
7407 TTL 集电极开路六正相高压驱动器
7408 TTL 2输入端四与门
7409 TTL 集电极开路2输入端四与门
7410 TTL 3输入端3与非门
74107 TTL 带清除主从双J-K触发器
74109 TTL 带预置清除正触发双J-K触发器
7411 TTL 3输入端3与门
74112 TTL 带预置清除负触发双J-K触发器
7412 TTL 开路输出3输入端三与非门
74121 TTL 单稳态多谐振荡器
74122 TTL 可再触发单稳态多谐振荡器
74123 TTL 双可再触发单稳态多谐振荡器
74125 TTL 三态输出高有效四总线缓冲门
74126 TTL 三态输出低有效四总线缓冲门
7413 TTL 4输入端双与非施密特触发器
74132 TTL 2输入端四与非施密特触发器
74133 TTL 13输入端与非门
74136 TTL 四异或门
74138 TTL 3-8线译码器/复工器
74139 TTL 双2-4线译码器/复工器
7414 TTL 六反相施密特触发器
74145 TTL BCD—十进制译码/驱动器
7415 TTL 开路输出3输入端三与门
74150 TTL 16选1数据选择/多路开关
74151 TTL 8选1数据选择器
74153 TTL 双4选1数据选择器
74154 TTL 4线—16线译码器
74155 TTL 图腾柱输出译码器/分配器
74156 TTL 开路输出译码器/分配器
74157 TTL 同相输出四2选1数据选择器
74158 TTL 反相输出四2选1数据选择器
7416 TTL 开路输出六反相缓冲/驱动器
74160 TTL 可预置BCD异步清除计数器
74161 TTL 可予制四位二进制异步清除计数器
74162 TTL 可预置BCD同步清除计数器
74163 TTL 可予制四位二进制同步清除计数器
74164 TTL 八位串行入/并行输出移位寄存器
74165 TTL 八位并行入/串行输出移位寄存器
74166 TTL 八位并入/串出移位寄存器
74169 TTL 二进制四位加/减同步计数器
7417 TTL 开路输出六同相缓冲/驱动器
74170 TTL 开路输出4×4寄存器堆
74173 TTL 三态输出四位D型寄存器
74174 TTL 带公共时钟和复位六D触发器
74175 TTL 带公共时钟和复位四D触发器
74180 TTL 9位奇数/偶数发生器/校验器
74181 TTL 算术逻辑单元/函数发生器
74185 TTL 二进制—BCD代码转换器
74190 TTL BCD同步加/减计数器
74191 TTL 二进制同步可逆计数器
74192 TTL 可预置BCD双时钟可逆计数器
74193 TTL 可预置四位二进制双时钟可逆计数器
74194 TTL 四位双向通用移位寄存器
74195 TTL 四位并行通道移位寄存器
74196 TTL 十进制/二-十进制可预置计数锁存器
74197 TTL 二进制可预置锁存器/计数器
7420 TTL 4输入端双与非门
7421 TTL 4输入端双与门
7422 TTL 开路输出4输入端双与非门
74221 TTL 双/单稳态多谐振荡器
74240 TTL 八反相三态缓冲器/线驱动器
74241 TTL 八同相三态缓冲器/线驱动器
74243 TTL 四同相三态总线收发器
74244 TTL 八同相三态缓冲器/线驱动器
74245 TTL 八同相三态总线收发器
74247 TTL BCD—7段15V输出译码/驱动器
74248 TTL BCD—7段译码/升压输出驱动器
74249 TTL BCD—7段译码/开路输出驱动器
74251 TTL 三态输出8选1数据选择器/复工器
74253 TTL 三态输出双4选1数据选择器/复工器
74256 TTL 双四位可寻址锁存器
74257 TTL 三态原码四2选1数据选择器/复工器
74258 TTL 三态反码四2选1数据选择器/复工器
74259 TTL 八位可寻址锁存器/3-8线译码器
7426 TTL 2输入端高压接口四与非门
74260 TTL 5输入端双或非门
74266 TTL 2输入端四异或非门
7427 TTL 3输入端三或非门
74273 TTL 带公共时钟复位八D触发器
74279 TTL 四图腾柱输出S-R锁存器
7428 TTL 2输入端四或非门缓冲器
74283 TTL 4位二进制全加器
74290 TTL 二/五分频十进制计数器
74293 TTL 二/八分频四位二进制计数器
74295 TTL 四位双向通用移位寄存器
74298 TTL 四2输入多路带存贮开关
74299 TTL 三态输出八位通用移位寄存器
7430 TTL 8输入端与非门
7432 TTL 2输入端四或门
74322 TTL 带符号扩展端八位移位寄存器
74323 TTL 三态输出八位双向移位/存贮寄存器
7433 TTL 开路输出2输入端四或非缓冲器
74347 TTL BCD—7段译码器/驱动器
74352 TTL 双4选1数据选择器/复工器
74353 TTL 三态输出双4选1数据选择器/复工器
74365 TTL 门使能输入三态输出六同相线驱动器
74365 TTL 门使能输入三态输出六同相线驱动器
74366 TTL 门使能输入三态输出六反相线驱动器
74367 TTL 4/2线使能输入三态六同相线驱动器
74368 TTL 4/2线使能输入三态六反相线驱动器
7437 TTL 开路输出2输入端四与非缓冲器
74373 TTL 三态同相八D锁存器
74374 TTL 三态反相八D锁存器
74375 TTL 4位双稳态锁存器
74377 TTL 单边输出公共使能八D锁存器
74378 TTL 单边输出公共使能六D锁存器
74379 TTL 双边输出公共使能四D锁存器
7438 TTL 开路输出2输入端四与非缓冲器
74380 TTL 多功能八进制寄存器
7439 TTL 开路输出2输入端四与非缓冲器
74390 TTL 双十进制计数器
74393 TTL 双四位二进制计数器
7440 TTL 4输入端双与非缓冲器
7442 TTL BCD—十进制代码转换器
74352 TTL 双4选1数据选择器/复工器
74353 TTL 三态输出双4选1数据选择器/复工器
74365 TTL 门使能输入三态输出六同相线驱动器
74366 TTL 门使能输入三态输出六反相线驱动器
74367 TTL 4/2线使能输入三态六同相线驱动器
74368 TTL 4/2线使能输入三态六反相线驱动器
7437 TTL 开路输出2输入端四与非缓冲器
74373 TTL 三态同相八D锁存器
74374 TTL 三态反相八D锁存器
74375 TTL 4位双稳态锁存器
74377 TTL 单边输出公共使能八D锁存器
74378 TTL 单边输出公共使能六D锁存器
74379 TTL 双边输出公共使能四D锁存器
7438 TTL 开路输出2输入端四与非缓冲器
74380 TTL 多功能八进制寄存器
7439 TTL 开路输出2输入端四与非缓冲器
74390 TTL 双十进制计数器
74393 TTL 双四位二进制计数器
7440 TTL 4输入端双与非缓冲器
7442 TTL BCD—十进制代码转换器
74447 TTL BCD—7段译码器/驱动器
7445 TTL BCD—十进制代码转换/驱动器
74450 TTL 16:1多路转接复用器多工器
74451 TTL 双8:1多路转接复用器多工器
74453 TTL 四4:1多路转接复用器多工器
7446 TTL BCD—7段低有效译码/驱动器
74460 TTL 十位比较器
74461 TTL 八进制计数器
74465 TTL 三态同相2与使能端八总线缓冲器
74466 TTL 三态反相2与使能八总线缓冲器
74467 TTL 三态同相2使能端八总线缓冲器
74468 TTL 三态反相2使能端八总线缓冲器
74469 TTL 八位双向计数器
7447 TTL BCD—7段高有效译码/驱动器
7448 TTL BCD—7段译码器/内部上拉输出驱动
74490 TTL 双十进制计数器74491 TTL 十位计数器
74498 TTL 八进制移位寄存器
7450 TTL 2-3/2-2输入端双与或非门
74502 TTL 八位逐次逼近寄存器
74503 TTL 八位逐次逼近寄存器
7451 TTL 2-3/2-2输入端双与或非门
74533 TTL 三态反相八D锁存器
74534 TTL 三态反相八D锁存器
7454 TTL 四路输入与或非门
74540 TTL 八位三态反相输出总线缓冲器
7455 TTL 4输入端二路输入与或非门
74563 TTL 八位三态反相输出触发器
74564 TTL 八位三态反相输出D触发器
74573 TTL 八位三态输出触发器
74574 TTL 八位三态输出D触发器
74645 TTL 三态输出八同相总线传送接收器
74670 TTL 三态输出4×4寄存器堆
7473 TTL 带清除负触发双J-K触发器
7474 TTL 带置位复位正触发双D触发器
7476 TTL 带预置清除双J-K触发器
7483 TTL 四位二进制快速进位全加器
7485 TTL 四位数字比较器
7486 TTL 2输入端四异或门
7490 TTL 可二/五分频十进制计数器
7493 TTL 可二/八分频二进制计数器
7495 TTL 四位并行输入\输出移位寄存器
7497 TTL 6位同步二进制乘法器
常用74系列标准数字电路的中文名称资料
器件代号 器件名称 74 74LS 74HC
00 四2输入端与非门 √ √ √
01 四2输入端与非门(OC) √ √
02 四2输入端或非门 √ √ √
03 四2输入端与非门(OC) √ √
04 六反相器 √ √ √
05 六反相器(OC) √ √
06 六高压输出反相器(OC,30V) √ √
07 六高压输出缓冲,驱动器(OC,30V) √ √ √
08 四2输入端与门 √ √ √
09 四2输入端与门(OC) √ √ √
10 三3输入端与非门 √ √ √
11 三3输入端与门 √ √
12 三3输入端与非门(OC) √ √ √
13 双4输入端与非门 √ √ √
14 六反相器 √ √ √
15 三3输入端与门 (OC) √ √
16 六高压输出反相器(OC,15V) √
17 六高压输出缓冲,驱动器(OC,15V) √
20 双4输入端与非门 √ √ √
21 双4输入端与门 √ √ √
22 双4输入端与非门(OC) √ √
25 双4输入端或非门(有选通端) √ √ √
26 四2输入端高压输出与非缓冲器 √ √ √
27 三3输入端或非门 √ √ √
28 四2输入端或非缓冲器 √ √ √
30 8输入端与非门 √ √ √
32 四2输入端或门 √ √ √
33 四2输入端或非缓冲器(OC) √ √
37 四2输入端与非缓冲器 √ √
38 四2输入端与非缓冲器(OC) √ √
40 双4输入端与非缓冲器 √ √ √
42 4线-10线译码器(BCD输入) √ √
43 4线-10线译码器(余3码输入) √
44 4线-10线译码器(余3葛莱码输入) √
48 4线-7段译码器 √
49 4线-7段译码器 √
50 双2路2-2输入与或非门 √ √ √
51 2路3-3输入,2路2-2输入与或非门 √ √ √
52 4路2-3-2-2输入与或门 √
53 4路2-2-2-2输入与或非门 √
54 4路2-3-3-2输入与或非门 √ √
55 2路4-4输入与或非门 √
60 双4输入与扩展器 √ √
61 三3输入与扩展器 √
62 4路2-3-3-2输入与或扩展器 √
64 4路4-2-3-2输入与或非门 √
65 4路4-2-3-2输入与或非门(OC) √
70 与门输入J-K触发器 √
71 与或门输入J-K触发器 √
72 与门输入J-K触发器 √
74 双上升沿D型触发器 √ √
78 双D型触发器 √ √
85 四位数值比较器 √
86 四2输入端异或门 √ √ √
87 4位二进制原码/反码 √
95 4位移位寄存器 √
101 与或门输入J-K触发器 √
102 与门输入J-K触发器 √
107 双主-从J-K触发器 √
108 双主-从J-K触发器 √
109 双主-从J-K触发器 √
110 与门输入J-K触发器 √
111 双主-从J-K触发器 √ √
112 双下降沿J-K触发器 √
113 双下降沿J-K触发器 √
114 双下降沿J-K触发器 √
116 双4位锁存器 √
120 双脉冲同步驱动器 √
121 单稳态触发器 √ √ √
122 可重触发单稳态触发器 √ √ √
123 可重触发双稳态触发器 √ √ √
125 四总线缓冲器 √ √ √
126 四总线缓冲器 √ √ √
128 四2输入端或非线驱动器 √ √ √
132 四2输入端与非门 √ √ √[论坛] 为什么要选用CPUVIEW?2007-11-29
2007-12-02 00:19:14
51定时器产生PWM(转贴)
2007-11-28 21:52:23
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